On-line Testing for FPGA

This paper focuses on the on-line error detection in circuits implemented in FPGAs. We have used error detection codes to ensure the self-checking property. A fault in a given combinational circuit has to be detected and signalized at the time of its appearance and before the further distribution of errors. Hence a safe operation of the designed system is guaranteed. The check bits generator and the checker were added to the original combinational circuit to detect an error during normal circuit operation called concurrent error detection and to ensure the Totally Self-Checking property. Only combinational circuits are considered. The benchmarks used in this work in order to compute a quality of the used code, are described by equations instead of tables, mainly used. All of our experiments assume their XILINX FPGA implementation.